The unit for data transmission defined by a communication protocol is referred to as “frame”. A frame can have a variety of field structures for the part of the frame before a data field thereof. For example, frames can be classified, in structure, into two or more types according to whether or not the frames have a break field in its head portion, and whether or not the frames have a control field fitting for the communication protocol next to the head portion. Frames of the type having the control field can be further classified into two or more types according to the format of definition of the control field, and likewise classified into two or more types according to the format of definition of an address of an address field. Conventionally, software programs have been used to cope with various communication protocols different from one another in field structure. For example, in application to a certain network system, to cope with the format of frames is made possible by making CPU execute a software program for analyzing control and address fields of frames according to the network protocol thereof. Hence, on receipt of a frame, a serial interface circuit concerned makes a request to CPU for interruption, and CPU analyzes control and address fields of the received frame. If the frame in question is directed to itself, the interface circuit continues processing the data field. If not, the circuit stops processing the data field.
Japanese published unexamined patent application No. JP-A-2008-77125 discloses an interface circuit arranged to reduce the load on CPU, which is required for a serial interface to judge a preamble and a header. The interface circuit adopts the following procedure which includes: capturing incoming transmitted data in a shift register bit by bit; storing, in FIFO register, reference data corresponding to predetermined data, such as a preamble and header, which are expected to be included in incoming transmitted data; comparing a value of FIFO register with a value of the shift register, and if they match up with each other, transferring the transmitted data in the shift register to a data register. For instance, if it is assumed that the unit of data processing by CPU is eight bits (equal to one byte), a shift register has a number of stages corresponding to a multiple of the processing unit in quantity such as an eight-bit. FIFO register is composed of: an eight-bit input register to which eight bits of known data are input in synchronization with the receive action by the shift register; and an eight-bit output register which stores data of the input register and outputs the data to a comparator in turn. Write on the input register is performed by CPU.